This disclosure relates to one-time programmable bitcell, and more specifically to a one-time programmable bitcell that uses a diode under the anti-fuse gate instead of a select device.
As the semiconductor industry continues to integrate more and more devices onto a single chip, the need for One Time Programmable (OTP) memory integrated into various CMOS processes is needed. OTP memory bitcells typically include a select device and an anti-fuse device connected in series. The select device and anti-fuse device both have gate oxides, and the anti-fuse device has a much thinner gate oxide than the select device. The difference in the thickness of the gate oxides is critical for the bitcell to operate. The select device must be able to sustain, for a brief period, a voltage that is sufficient to rupture the thin gate oxide in the same period. If two gate oxide thicknesses are not available in a given process, the existing OTP solutions do not work.
Advanced CMOS processes are moving from silicon dioxide (SiO2) gate dielectrics to gate dielectrics that are a composite of SiO2 and a higher dielectric constant (referred to as “high-κdielectrics,” where κ is the dielectric constant). Many advanced CMOS processes have two gate dielectric thicknesses. The core or thin gate dielectric is made with an extremely thin SiO2 layer under a high-κ dielectric. The I/O or thick gate dielectric is made with a thicker SiO2 layer and the same high-κ dielectric on top of it. In such processes, the high-κ dielectric included in the core gate oxide might not be suitable for an anti-fuse gate in a typical OTP bitcell.
Most gate dielectrics in silicon processes have traps. Depending on the context, a “trap” can refer to both active and latent dielectric defects, or refer only to the active defects. When SiO2 is grown on a silicon substrate, there is a crystal mismatch due to oxygen atom being smaller than the silicon atom. The oxygen and silicon ideal bond angle is 120°. As a result of the lattice mismatch between the silicon substrate and the SiO2 grown on it, the SiO2 layer is amorphous with varying bond angles. The further the bond angle is from 120°, the weaker the bond will be. Silicon-to-oxygen bonds almost never form when the bond angle is less than 100° or greater than 170°. When the bond angle is outside of this range, the oxygen atom will not bond to the silicon, and a silicon atom will replace an oxygen atom in the lattice. Because of this replacement, the ratio of oxygen to silicon is less than 2:1 (as expected for SiO2), and may be more like 1.99:1. When a silicon-to-silicon bond is formed inside a SiO2 region, that bond is much weaker than the silicon-to-oxygen bonds. The silicon-to-silicon bond can be broken by a high electric field, or by current passing through the dielectric. The silicon-to-silicon bond also re-form through annealing, or healing with enough thermal energy or heat. When the silicon-to-silicon bond is intact, it acts like a dielectric. The intact silicon-to-silicon bond is referred to as latent defect, e-prime precursor, latent trap, or inactive trap. When the silicon-to-silicon bond is broken, it acts like a tiny conductive spot; an electron can move to, or “hop into,” the conductive spot, stay some time, and then move or “hop” to another conductive spot. When the bond is broken, it is referred to as an active defect, e-prime center, or active trap. The high-κ dielectric materials used in advanced CMOS processes typically have even more traps than SiO2.
Typically, when a gate oxide anti-fuse ruptures, the current is high enough for self-heating to cause a conductive filament to form through the gate oxide, shorting the conductive gate material to the silicon substrate below the gate oxide. This is known as gate rupture or hard breakdown. However, if the trap density in a dielectric is high, then soft breakdown is possible. Soft breakdown occurs when enough traps become active that the leakage current mimics the result of a rupture. The difference between hard and soft breakdown is that soft breakdowns, unlike hard breakdowns, can anneal (i.e., heal). During a typical OTP anti-fuse rupture, the electric fields and current through the dielectric is high enough to first activate all or almost all of the traps to create a preferred localized current path, and then the high current heats the localized spot sufficiently to form a silicon filament through the gate dielectric. If the current is high enough to activate the traps but not high enough to form a filament, the activated traps can anneal or heal at room temperature, causing an anti-fuse that should have been ruptured to flip to an intact state. This means if the trap density is high enough, the thin gate dielectrics in some advanced CMOS processes are not reliable enough for use as OTP gate rupture anti-fuses. In these processes, it might be necessary to use the thick gate dielectric for the anti-fuse element. The thicker oxide relies on the SiO2 portion of the gate stack being thick enough and having low enough trap density to avoid soft break down. If the thick gate dielectric is used for the anti-fuse element, the typical OTP architecture with two gates of different thicknesses is no longer suitable.
Another problem for OTP gate oxide rupture scaling is that as feature sizes get smaller, the thin gate oxide area gets smaller. In very small areas it might be possible not to have any silicon-silicon traps. The lattice mismatch causes some trap density, but in a given very small area there might not be any traps. This results in fraction of the anti-fuses that require a much higher voltage to rupture. The voltage and current required to rupture these anti-fuses without traps might exceed the capabilities of the select device. In these technologies, a bitcell without a select device might be needed.
For gate oxide rupture OTP bitcells to form a good filament during rupture, a high current is needed. In very small bitcells, the select device can limit the current to below what is needed to cause a soft break down to a hard breakdown. In some technologies, a bitcell with either a much larger select device or a bitcell without a select device might be needed.
There are other reasons that an OTP bitcell with two gate oxides may not be suitable or possible. For example, certain processes only have one gate oxide available. For example, some BCD (Bipolar complementary metal-oxide-semiconductor (CMOS) double-diffused metal-oxide-semiconductor (DMOS)) processes have either only one gate oxide, or two gate oxides where the second gate oxide is not usable. An example of this would be a 0.18 μm 5V/40V process. In this process, the 40V DMOS device uses a 5V gate oxide to control the device. The drain is engineered to handle 40V with a 5V gate controlling it, so only one gate oxide is needed. If a 5V/40V process does have a 40V gate oxide, the 40V device is so large that using it as a select device may result in an unacceptably large bitcell.
Floating gate many times programmable (MTP) non-volatile memories (NVM) typically use Fowler-Nordheim tunneling (“FN-tunneling”) for either erasing or programming, or both. Many high endurance, high reliability floating gate NVMs use an electric field of around 10 MV/cm across the gate oxide to program or erase a floating gate in the specified time. There are floating gate NVMs available that can achieve 100,000 program/erase cycles, and more than 10 years' data retention using FN-Tunnel voltages of 10 MV/cm or higher.
OTP gate oxide memories typically use an electric field of around 30 MV/cm to rupture anti-fuses in the gate oxide. This 30 MV/cm is a compromise voltage that balances the demands of programming speeds and stresses on the chip. Many applications program the OTP memory at test, and testing time is a significant portion of the total manufacturing cost of a chip. Using higher voltages reduces the programming time, thus reducing test costs and overall manufacturing cost.